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1 copyright ? cirrus logic, inc. 2004 (all rights reserved) http://www.cirrus.com cs4397 24-bit, multi-standard d/a converter for digital audio features 24 bit conversion up to 192 khz sample rates 120 db dynamic range -100 db thd+n supports pcm, dsd and external interpolation filters advanced dynamic-element matching low clock jitter sensitivity digital de-emphasis for 32 khz, 44.1 khz and 48 khz external reference input description the cs4397 is a complete high performance 24-bit 48/96/192 khz stereo digital-to-analog conversion sys- tem. the device includes a digital interpolation filter followed by a oversampled multi-bit delta-sigma modula- tor which drives dynamic-element-matching (dem) selection logic. the output from the dem block controls the input to a multi-element switched capacitor dac/low- pass filter, with fully-differential outputs. this multi-bit ar- chitecture features significantly lower out-of-band noise and jitter sensitivity than traditional 1-bit designs, and the advanced dem guarantees low noise and distortion at all signal levels. ordering information CS4397-KS -10 to 70 c 28-pin plastic soic CS4397-KSz -10 to 70 c 28-pin plastic soic lead free cdb4397 evaluation board i sclk mclk m4 lrck sdata aoutl+ aoutr+ serial interface and format select interpolation soft mute ? modulator dynamic de-emphasis switched aoutl- aoutr- filt+ filter interpolation filter filter multi-bit ? modulator multi-bit element matching logic dynamic element matching logic capacitor-dac and filter switched capacitor-dac and filter vref cmout filt- voltage reference hardware mode control clock divider (control port) (ad0/cs) m3 m2 (ad1/cdin) (scl/cclk) m1 m0 (sda/cdout) reset mutec mute sep ?04 ds333f1
cs4397 2 ds333f1 table of contents 1.0 characteristics/specifications ..................................................................... 4 analog characteristics................................................................................... 4 dynamic performance - single speed mode - fs equal to 48 khz ...................... 4 dynamic performance - double speed mode - fs equal to 96 khz .................... 4 dynamic performance - quad-speed mode - fs equal to 192 khz ..................... 4 analog characteristics................................................................................... 5 power supplies .................................................................................................... 5 analog output ...................................................................................................... 5 combined digital and on-chip analog filter response - single speed mode .... 6 combined digital and on-chip analog filter response - double speed mode ... 6 combined digital and on-chip analog filter response - quad-speed mode ..... 6 analog characteristics - dsd mode ............................................................ 7 dynamic performance - dsd mode ..................................................................... 7 analog output - dsd mode ................................................................................. 7 combined digital and on-chip analog filter response - dsd mode .................. 7 analog characteristics - 8x interpolator mode .................................. 8 dynamic performance mode ................................................................................ 8 analog output ...................................................................................................... 8 combined digital and on-chip analog filter response - 8x interpolator mode ... 8 digital characteristics.................................................................................... 9 absolute maximum ratings .............................................................................. 9 recommended operating conditions .......................................................... 9 switching characteristics ........................................................................... 10 dsd - switching characteristics ................................................................ 11 8x interpolator - switching characteristics....................................... 12 switching characteristics - control port ........................................... 13 i 2 c? mode ......................................................................................................... 13 spi mode ........................................................................................................... 14 2.0 typical connection diagram .......................................................................... 15 3.0 register description ........................................................................................ 16 3.1 differential dc offset calibration ........................................................................ 16 3.2 soft mute ........................................................................................................... 16 3.3 mode select ....................................................................................................... 17 3.4 power down ...................................................................................................... 17 4.0 pin description - pcm mode .............................................................................. 18 5.0 pin description - dsd mode .............................................................................. 23 6.0 pin description - 8x interpolator mode .................................................... 24 7.0 applications .......................................................................................................... 25 7.1 recommended power-up sequence ................................................................. 25 8.0 control port interface .................................................................................. 26 8.1 spi mode ........................................................................................................... 26 8.2 i 2 c mode ........................................................................................................... 26 8.2 memory address pointer (map) ....................................................................... 26 9.0 parameter definitions ...................................................................................... 33 10.0 references .......................................................................................................... 33 11.0 package dimensions ........... .............................................................................. 34
cs4397 ds333f1 3 table of figures figure 1. serial audio input timing ......................................................................... 10 figure 2. direct stream digital - serial audio input timing ..................................... 11 figure 3. serial audio input timing ......................................................................... 12 figure 4. i2c control port timing ............................................................................ 13 figure 5. spi control port timing ........................................................................... 14 figure 6. typical connection diagram - hardware mode (control port mode) ....... 15 figure 7. control port timing, i 2 c mode ................................................................. 27 figure 8. control port timing, spi mode ................................................................ 27 figure 9. single-speed transition band .................................................................. 29 figure 10.single-speed stopband rejection ............................................................ 29 figure 11.single-speed transition band .................................................................. 29 figure 12.single-speed frequency response ......................................................... 29 figure 13.double-speed stopband .......................................................................... 29 figure 14.double-speed transition band ................................................................. 29 figure 15.double-speed transition band ................................................................. 29 figure 16.double-speed frequency response ........................................................ 29 figure 17.quad-speed stopband rejection ............................................................. 30 figure 18.quad-speed transition band ................................................................... 30 figure 19.quad-speed transition band ................................................................... 30 figure 20.quad-speed frequency response .......................................................... 30 figure 21.8x interpolator stop band ........................................................................ 30 figure 22.8x interpolator transition band ................................................................ 30 figure 23.8x interpolator transition band ................................................................ 30 figure 24.8x interpolator frequency response ....................................................... 30 figure 25.dsd frequency response ...................................................................... 31 figure 26.dsd transition band ............................................................................... 31 figure 27.dsd transition band ............................................................................... 31 figure 28.de-emphasis curve ................................................................................. 31 figure 29.format 0, left justified ............................................................................. 32 figure 30.format 1, i 2 s ........................................................................................... 32 figure 31.format 2, right justified, 16-bit data ...................................................... 32 figure 32.format 3, right justified, 24-bit data ...................................................... 32 figure 33.format 4, 8x interpolator mode ................................................................ 32 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ ?the i 2 c-bus specification: version 2.0? philips semiconductors, december 1998. http://www.semiconductors.philips.com preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi ded ?as is? without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http ://www.cirrus.com.
cs4397 4 ds333f1 1.0 characteristics/specifications analog characteristics (t a = 25 c; logic "1" = vd = 5 v; va = 5v; logic "0" = dgnd; full-scale output sine wave, 997 hz; mclk = 12.288 mhz; sclk = 3.072 mhz, measurement bandwidth 10 hz to 20 khz, unless otherwise specified. test load r l = 1 k ? , c l = 10 pf) notes: 1. triangular pdf dithered data. 2. performance limited by 16-bit quantization noise. parameter symbol min typ max unit dynamic performance - single speed mode - fs equal to 48 khz dynamic range (note 1) 24-bit unweighted a-weighted 16-bit unweighted (note 2) a-weighted tbd tbd - - 117 120 95 98 - - - - db db db db total harmonic distortion + noise (note 1) 24-bit 0 db -20 db -60 db 16-bit 0 db (note 2) -20 db -60 db thd+n - - - - - - -100 -97 -57 -95 -75 -35 tbd tbd tbd - - - db db db db db db dynamic performance - double speed mode - fs equal to 96 khz dynamic range (note 1) 24-bit unweighted a-weighted 40 khz bandwidth unweighted 16-bit unweighted (note 2) a-weighted tbd tbd tbd - - 117 120 114 92 98 - - - - - db db db db db total harmonic distortion + noise (note 1) 24-bit 0 db -20 db -60 db 16-bit 0 db (note 2) -20 db -60 db thd+n - - - - - - -100 -97 -57 -95 -75 -35 tbd tbd tbd - - - db db db db db db dynamic performance - quad-speed mode - fs equal to 192 khz dynamic range (note 1) 24-bit unweighted a-weighted 40 khz bandwidth unweighted 16-bit unweighted (note 2) a-weighted tbd tbd tbd - - 117 120 114 92 98 - - - - - db db db db db total harmonic distortion + noise (note 1) 24-bit 0 db -20 db -60 db 16-bit 0 db (note 2) -20 db -60 db thd+n - - - - - - -100 -97 -57 -95 -75 -35 tbd tbd tbd - - - db db db db db db
cs4397 ds333f1 5 analog characteristics (continued) notes: 3. valid with the recommended capacitor values on filt+ and cmout as shown in figure 1. increasing the capacitance will also increase the psrr. parameter symbol vd = 3 v vd = 5 v unit power supplies min typ max min typ max supply current normal operation va = 5 v normal operation power-down state i a i d i d + i a - - - 20 tbd 60 tbd tbd - - - - 20 tbd 30 tbd tbd - ma ma a power dissipation normal operation va = 5 v power-down - - tbd 0.3 tbd - - - tbd 0.3 tbd - mw mw power supply rejection ratio (1 khz) (note 3) (120 hz) psrr - - 60 40 - - - - 60 40 - - db db parameter symbol min typ max unit analog output full scale differential output voltage tbd 1.4vref tbd vpp common mode voltage - 0.5vref - vdc interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c differential dc offset - 2.0 tbd mv ac-load resistance r l 1--k ? load capacitance c l - - 100 pf interchannel isolation (1 khz) - 90 - db
cs4397 6 ds333f1 analog characteristics (continued) notes: 4. response is clock dependent and will scale with fs. note that the response plots ( figures 9-28 ) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 5. for single-speed mode, the measurement bandwidth is 0.5465 fs to 1.4 fs. for double-speed mode, the measurement bandwidth is 0.570 fs to 1.4 fs. for quad-speed mode, the measurement bandwidth is 0.635 fs to 1.3 fs. 6. group delay for fs=48 khz 37/48 khz=770 s 7. de-emphasis is available only in single speed mode. parameter symbol min typ max unit combined digital and on-chip analog filter response - single speed mode passband (note 4) to -0.1 db corner to -3 db corner - - - - 0.470 0.492 fs fs frequency response 10 hz to 20 khz -.020 - +0.015 db passband ripple - - 0.0001 db stopband .5465 - - fs stopband attenuation (note 5) 102 - - db group delay (note 6) tgd - 37/fs - s de-emphasis error (note 7) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.10 0.10 0.13 db db db combined digital and on-chip analog filter response - double speed mode passband (note 4) to -0.1 db corner to -3 db corner 0 0 - - 0.448 0.486 fs fs frequency response 10 hz to 20 khz -0.017 - 0.035 db passband ripple - - 0.0008 db stopband .570 - - fs stopband attenuation (note 5) 82 - - db group delay tgd - 20/fs - s combined digital and on-chip analog filter response - quad-speed mode passband (note 4) to -0.1 db corner to -3 db corner - - - - 0.385 0.472 fs fs frequency response 10 hz to 20 khz 0 - +0.015 db passband ripple - - 0.00065 db stopband 0.635 - - fs stopband attenuation (note 5) 83 - - db group delay tgd - 11/fs - s
cs4397 ds333f1 7 analog characteristics - dsd mode (t a = 25 c; logic "1" = vd = 5 v; va = 5v; logic "0" = agnd; full-scale output sine wave, 997 hz; measurement bandwidth 10 hz to 20 khz, unless other- wise specified. test load r l = 1 k ? , c l = 10 pf) notes: 8. assumes a dsd modulation index of 0.7. parameter symbol min typ max unit dynamic performance - dsd mode dynamic range (note 1) unweighted a-weighted tbd tbd 117 120 - - db db total harmonic distortion + noise (note 1) 0 db -20 db -60 db thd+n - - - -100 -94 -54 tbd tbd tbd db db db analog output - dsd mode full scale differential output voltage (note 8) tbd 1.2vref tbd vpp common mode voltage - 0.5vref - vdc interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c differential dc offset - 2.0 tbd mv combined digital and on-chip analog filter response - dsd mode passband (note 4) to -0.1 db corner to -3 db corner - - - - 0.95 2.70 fs fs frequency response 10 hz to 20 khz -0.013 - 0 db group delay tgd - 0.2/fs - s
cs4397 8 ds333f1 analog characteristics - 8x interpolator mode (t a = 25 c; logic "1" = vd = 5 v; va = 5v; logic "0" = agnd; full-scale output sine wave, 997 hz; base band fs = 48 khz, sclk = 6.144 mhz, measurement bandwidth 10 hz to 20 khz, unless otherwise specified. test load r l = 1 k ? , c l = 10 pf) notes: 9. measurement bandwidth is 6.08 to 9.6 fs parameter symbol min typ max unit dynamic performance mode dynamic range (note 1) unweighted a-weighted tbd tbd 117 120 - - db db total harmonic distortion + noise (note 1) 0 db -20 db -60 db thd+n - - - -100 -97 -57 tbd tbd tbd db db db analog output full scale differential output voltage tbd 0.7vref tbd vpp common mode voltage - 0.5vref - vdc interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c differential dc offset - 2.0 tbd mv combined digital and on-chip analog filter response - 8x interpolator mode passband (note 4) to -0.1 db corner to -3 db corner - - - - 2.10 3.52 fs fs frequency response 10 hz to 20 khz -0.0008 - 0 db passband ripple - - 0 db stopband 6.08 - - fs stopband attenuation (note 9) 56 - - db group delay tgd - 0.9/fs - s
cs4397 ds333f1 9 digital characteristics (t a = 25c; vd = 3.0v - 5.25v) absolute maximum ratings (agnd = 0 v, all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (dgnd = 0v; all voltages with respect to ground) parameters symbol min typ max units high-level input voltage vd = 5 v vd = 3 v v ih 2.0 2.0 - - - - v v low-level input voltage vd = 5 v vd = 3 v v il - - - - 0.8 0.8 v v input leakage current i in --10 a input capacitance - 8 - pf maximum mutec drive current - 3 - ma parameter symbol min max unit dc power supply: positive analog positive digital reference voltage va vd vref -0.3 -0.3 -0.3 6.0 6.0 va v v v input current, any pin except supplies i in -10ma digital input voltage v ind -0.3 (vd)+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameter symbol min typ max unit dc power supply: positive digital positive analog reference voltage vd va vref 3.0 4.75 tbd 3.3 5.0 5.0 5.25 5.25 va v v v specified temperature range t a -10 - 70 c
cs4397 10 ds333f1 switching characteristics (t a = -10 to 70c; logic 0 = agnd = dgnd; logic 1 = vd = 5.25 to 3.0 volts; c l =20pf) parameter symbol min typ max unit input sample rate (single-speed mode) (double-speed mode) (quad-speed mode) fs fs fs 16 50 100 - - - 50 100 200 khz khz khz lrck duty cycle 45 50 55 % mclk frequency (single-speed 256 fs, double speed 128 fs or quad-speed 64 fs) 4.096 - 12.8 mhz mclk frequency (single-speed 384 fs, double speed 192 fs or quad-speed, 96 fs 6.144 - 19.2 mhz mclk frequency (single-speed 512 fs, double speed 256 fs or quad-speed, 128 fs 8.192 - 25.6 mhz mclk frequency (single-speed 768 fs, double speed 384 fs or quad-speed, 192 fs 12.288 - 38.4 mhz mclk duty cycle 40 50 60 % sclk frequency (single-speed mode) (double-speed mode) (quad-speed mode) - - - - - - 256fs 128fs 64fs hz hz hz sclk rising to lrck edge delay t slrd 20 --ns sclk rising to lrck edge setup time t slrs 20 --ns sdata valid to sclk rising setup time t sdlrs 20 --ns sclk rising to sdata hold time t sdh 20 --ns slrs t slrd t sdlrs t sdh t sdata sclk lrck figure 1. serial audio input timing
cs4397 ds333f1 11 dsd - switching characteristics (t a = -10 to 70c; logic 0 = agnd = dgnd; logic 1 = vd = 5.25 to 3.0 volts; c l =20pf) parameter symbol min typ max unit input bit rate per channel (64x oversampled) (128x oversampled) 1.024 2.048 - - 3.2 6.4 mb/s mb/s master clock frequency (clkmode = 0) (clkmode = 1) 4.096 6.144 - - 12.8 19.2 mhz mhz mclk duty cycle (all dsd modes) 40 - 60 % dsd_sclk pulse width low t sclkl 20 --ns dsd_sclk pulse width high t sclkh 20 --ns dsd_sclk frequency (64x oversampled) (128x oversampled) 1.024 2.048 - - 3.2 6.4 mhz mhz dsd_li_r valid to dsd_sclk rising setup time t sdlrs 20 --ns dsd_sclk rising to dsd_l or dsd_r hold time t sdh 20 --ns sclkh t sclkl t dsd_l, dsd_r dsd_sclk sdlrs t sdh t figure 2. direct stream digital - serial audio input timing
cs4397 12 ds333f1 8x interpolator - switching characteristics (t a = -10 to 70c; logic 0 = agnd = dgnd; logic 1 = vd = 5.25 to 3.0 volts; c l =20pf) notes: 10. fs refers to the input sample rate to the digital-to-analog converter, i.e. fs = 44.1 khz 8 = 352.8 khz. parameter symbol min typ max unit input sample rate (note 10) fs 128 - 400 khz mclk frequency (mclk = 32fs) (mclk = 48fs) (mclk = 64fs) (mclk = 96fs) 4.096 6.144 8.192 12.288 - - - - 12.8 19.2 25.6 28.4 mhz mhz mhz mhz mclk duty cycle 40 - 50 % wcki duty cycle 25 - 75 % bcki frequency 32xfs mhz bcki rising to wcki edge delay t slrd 20 --ns bcki rising to wcki edge setup time t slrs 20 --ns sdata valid to bcki rising setup time t sdlrs 20 --ns bcki rising to dil/dir hold time t sdh 20 --ns sclkh t slrs t slrd t sdlrs t sdh t sclkl t dil/dir bcki wcki figure 3. serial audio input timing
cs4397 ds333f1 13 switching characteristics - control port (t a = 25 c; vd = 5.25 v to 3.0 volts; inputs: logic 0 = agnd, logic 1 = vd, c l = 30 pf) notes: 11. data must be held for sufficient time to bridge the 300 ns transition time of scl. parameter symbol min max unit i 2 c ? mode scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 11) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of both sda and scl lines t r -1s fall time of both sda and scl lines t f - 300 ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 4. i 2 c control port timing
cs4397 14 ds333f1 switching characteristics - control port (t a = 25 c; vd = 5.25 v to 3.0 volts; inputs: logic 0 = agnd, logic 1 = vd, c l = 30 pf) notes: 12. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 13. data must be held for sufficient time to bridge the transition time of cclk. 14. for f sck < 1 mhz parameter symbol min max unit spi mode cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 12) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 13) t dh 15 - ns rise time of cclk and cdin (note 14) t r2 - 100 ns fall time of cclk and cdin (note 14) t f2 - 100 ns cclk falling to cdout valid t ov 45 ns t r2 t f2 t dsu t dh t sch t scl cs cclk t css t csh t spi t srs rst t ov cdin cdout figure 5. spi control port timing
cs4397 ds333f1 15 2.0 typical connection diagram sclk audio data processor external clock mclk agnd aoutr+ cs4397 sdata va aoutr- +5v analog 0.1 f + 1 f mode select (control port) m1 (gnd) m0 (sda/cdout) aoutl- aoutl+ dgnd vd mute analog conditioning analog conditioning 7 22 24 23 19 20 18 9 1 15 13 11 12 4 14 5 m2 (scl/cclk) lrck 1.0 f + rst 10 m3 (ad1/cdin) m4 (ad0/cs) 2 3 25 0.1 f 5.6 f 0.1 f 100 f 26 27 vref filt+ filt- +5v analog 28 6 21 mutec 0.1 f 8 17 + + cmout vd 0.1 f 16 c/h +5 to +3 v digital figure 6. typical connection diagram - hardware mode (control port mode)
cs4397 16 ds333f1 3.0 register description 3.1 differential dc offset calibration mode control register (address 01h) access: r/w in i 2 c and spi. default: 0 - disabled function: enabling this function will initiate a calibration to minimize the differential dc offset. this function will be automatically reset following completion of the calibration sequence. 3.2 soft mute mode control register (address 01h) access: r/w in i 2 c and spi. default: 0 - enabled function: the analog outputs will ramp to a muted state when enabled. the ramp requires 1152 left/right clock cy- cles in single speed, 2304 cycles in double speed and 4608 cycles in quad speed mode. the bias volt- age on the outputs will be retained and mutec will go low at the completion of the ramp period. the analog outputs will ramp to a normal state when this function transitions from the enabled to disabled state. the ramp requires 1152 left/right clock cycles in single speed, 2304 cycles in double speed and 4608 cycles in quad s peed mode. the mutec will go high immediately on disabling of mute . 76543210 cal mute m4 m3 m2 m1 m0 pdn cal mode 0 disabled : cal complete 1 enabled : cal initiated table 1. 76543210 cal mute m4 m3 m2 m1 m0 pdn mute mode 0 enabled 1 disabled table 2.
cs4397 ds333f1 17 3.3 mode select mode control register (address 01h) access: r/w in i 2 c and spi. default: 00000 function: the mode select pins determine the operational mode of the device as detailed in tables 9-14. the op- tions include: selection of the digital interface format which determines the required relationship between the left/right clock, serial clock and serial data as detailed in figures 29-33 selection of the standard 15 s/50 s digital de-emphasis filter response, figure 28, which requires re- configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 khz sample rates. selection of the appropriate clocking mode to match the input sample rates. access to the direct stream digital mode access to the 8x interpolation input mode 3.4 power down mode control register (address 01h) access: r/w in i 2 c and spi. default: 1 - powered down function: the analog and digital sections will be placed into a power-down mode when this function is enabled. this bit must be cleared to resume normal operation. 76543210 cal mute m4 m3 m2 m1 m0 pdn 76543210 cal mute m4 m3 m2 m1 m0 pdn pdn mode 0 disabled 1 enabled table 3.
cs4397 18 ds333f1 4.0 pin description - pcm mode reset - rst pin 1, input function: the device enters a low power mode and all internal state machines registers are reset when low. when high, the device will be in a normal operation mode . digital ground - dgnd pins 6 and 9, inputs function: digital ground reference. digital power - vd pins 7 and 8, input function: digital power supply. typically 5.0 to 3.0 vdc. master clock - mclk pin 10, input function: the master clock frequency must be either 256x, 384x, 512x or 768x the input sample rate in single speed mode; either 128x, 192x 256x or 384x the input sample rate in double speed mode; or 64x, 96x 128x or 192x the input sample rate in quad speed mode. tables 4-6 illustrate the standard audio sample rates and the required master clock frequencies. rst description 0 enabled 1 normal operation mode 1 2 3 4 5 6 7 8 9 10 11 12 5 1 2 6 28 27 26 25 24 23 22 21 20 19 18 17 13 14 16 15 reset rst vref voltage reference see description m4(ad0/cs ) filt+ reference filter see description m3(ad1/cdin) filt- reference ground see description m2(scl/cclk) cmout common modes voltage see description m0(sda/cdout) aoutl- differential output digital ground dgnd aoutl+ differential output digital power vd va analog power digital power vd agnd analog ground digital ground dgnd aoutr+ differential output master clock mclk aoutr- differential output serial clock sclk agnd analog ground left/right clock lrck mutec mute control serial data sdata c/h control port/hardware select see description m1 mute soft mute
cs4397 ds333f1 19 serial clock - sclk pin 11, input function: clocks individual bits of serial data into the sdata pin. the required relationship between the left/right clock, serial clock and serial data is defined by either the mode control byte in control port mode or the m0 - m4 pins in hardware mode. the options are detailed in figures 29-33 left/right clock - lrck pin 12, input function: the left/right clock determines which channel is currently being input on the serial audio data input, sdata. the frequency of the left/right clock must be at the input sample rate. audio samples in left/right sample pairs will be simultaneously output from the digital-to-analog converter whereas right/left pairs will exhibit a one sample period difference. the required relationship between the left/right clock, serial clock and serial data is defined by the mode control byte and the options are de- tailed in figures 29-33 serial audio data - sdata pin 13, input function: two's complement msb-first serial data is input on this pin. the data is clocked into sdata via the serial clock and the channel is determined by the left/right clock. the required relationship between the left/right clock, serial clock and serial data is defined by the mode control byte and the options are de- tailed inin figures 29-33 soft mute - mute pin 15, input function: the analog outputs will ramp to a muted state when enabled. the ramp requires 1152 left/right clock cy- sample rate (khz) mclk (mhz) 256x 384x 512x 768x 32 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 48 12.2880 18.4320 24.5760 36.8640 table 4. single speed (16 to 50 khz sample rates) common clock frequencies sample rate (khz) mclk (mhz) 128x 192x 256x 384x 64 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640 table 5. double speed (50 to 100 khz sample rates) common clock frequencies sample rate (khz) mclk (mhz) 64x 96x 128x 192x 176.4 11.2896 16.9344 22.5792 33.8688 192 12.2880 18.4320 24.5760 36.8640 table 6. quad speed (100 to 200 khz sample rates) common clock frequencies
cs4397 20 ds333f1 cles in single speed, 2304 cycles in double speed and 4608 cycles in quad speed mode. the bias volt- age on the outputs will be retained and mutec will go active at the completion of the ramp period. the analog outputs will ramp to a normal state when this function transitions from the enabled to disabled state. the ramp requires 1152 left/right clock cycles in single speed, 2304 cycles in double speed and 4608 cycles in quad s peed mode. the mutec will release immediately on setting mute = 1. the converter analog outputs will mute when enabled. the bias voltage on the outputs will be retained and mutec will go active during the mute period. control port / hardware mode select - c/h pin 16, input function: determines if the device will operate in eit her the hardware mode or control port mode. mute control - mutec pin 17, output function: the mute control pin goes low during power-up initialization, reset, muting, master clock to left/right clock frequency ratio is incorrect or power-down. this pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. use of mute control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. analog ground - agnd pins 18 and 21, inputs function: analog ground reference. differential analog outpus - aoutr- , aoutr+ and aoutl- , aoutl+ pins 19, 20, 23 and 24, outputs function: the full scale differential analog output level is specified in the analog characteristics specifications table. analog power - va pin 22, input function: power for the analog and reference circuits. typically 5vdc. mute description 0 enabled 1 normal operation mode c/h description 0 hardware mode enabled 1 control port mode enabled
cs4397 ds333f1 21 common mode voltage - cmout pin 25, output function: filter connection for internal bias voltage, typically 50% of vref. capacitors must be connected from cmout to analog ground, as shown in figure 6. cmout has a typical source impedence of 25 k ? and any current drawn from this pin will alter device performance reference ground - filt- pin 26, input function: ground reference for the internal sampling circuits. must be connected to analog ground. reference filter - filt+ pin 27, output function: positive reference for internal sampling circuits. external capacitors are required from filt+ to analog ground, as shown in figure 6. the recommended values will typically provide 60 db of psrr at 1 khz and 40 db of psrr at 120 hz. filt+ is not intended to supply external current. voltage reference input- vref pin 28, input function: analog voltage reference. typically 5vdc. hardware mode mode select - m0, m1, m2, m3, m4 pins 2, 3, 4, 5 and 14, inputs function: the mode select pins determine the operational mode of the device as detailed in tables 9-14. the op- tions include; selection of the digital interface format which determines the required relationship between the left/right clock, serial clock and serial data as detailed in figures 29-33 selection of the standard 15 s/50 s digital de-emphasis filter response, figure 28, which requires re- configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 khz sample rates. selection of the appropriate clocking mode to match the input sample rates. access to the direct stream digital mode access to the 8x interpolation input mode control port mode address bit 0 / chip select - ad0 / cs pin 2, input function: in i 2 c mode, ad0 is a chip address bit. cs is used to enable the control port interface in spi mode. the device will enter the spi mode at anytime a high to low transition is detected on this pin. once the device has entered the spi mode, it will remain until either the part is reset or undergoes a power-down cycle.
cs4397 22 ds333f1 address bit 1 / control data input - ad1/cdin pin 3, input function: in i 2 c mode, ad1 is a chip address bit. cdin is the control data input line for the control port interface in spi mode. serial control interface clock - scl/cclk pin 4, input function: in i 2 c mode, scl clocks the serial control data into or from sda/cdout. in spi mode, cclk clocks the serial data into ad1/cdin and out of sda/cdout. serial control data i/o - sda/cdout pin 5, input/output function: in i 2 c mode, sda is a data input/output. cdout is the control data output for the control port interface in spi mode. m1 - mode select pin 14, input function: this pin is not used in control port mode and must be terminated to ground.
cs4397 ds333f1 23 5.0 pin description - dsd mode master clock - mclk pin 10, input function: the master clock frequency must be either 4x or 6x the dsd data rate for 64x oversampled dsd data and 2x or 3x the dsd data rate for 128x oversampled dsd data, refer to table 7. clkmode pin 12, input function: this pin determines the allowable master clock to dsd data ratio as defined in table 7. dsd serial clock - dsd_sclk pin 11, input function: clocks the individual bits of the dsd audio data into the dsd_l and dsd_r pins. audio data - dsd_l and dsd_r pins 13 and 14, inputs function: direct stream digital audio data is clocked into dsd_l and dsd_r via the dsd serial clock. clkmode dsd over- sampling ratio 01 64x 4x 6x 128x 2x 3x table 7. mclk to dsd data rate clock ratios refer to pcm mode rst vref refer to pcm mode refer to pcm mode m4(ado/cs ) filt+ refer to pcm mode refer to pcm mode m3(ad1/cdin) filt- refer to pcm mode refer to pcm mode m2(scl/cclk) cmout refer to pcm mode refer to pcm mode m0(sda/cdout) aoutl- refer to pcm mode refer to pcm mode dgnd aoutl+ refer to pcm mode refer to pcm mode vd va refer to pcm mode refer to pcm mode vd agnd refer to pcm mode refer to pcm mode dgnd aoutr+ refer to pcm mode master clock mclk aoutr- refer to pcm mode dsd serial clock dsd_sclk agnd refer to pcm mode master clock mode clkmode mutec refer to pcm mode left channel data dsd_l c/h refer to pcm mode right channel data dsd_r mute refer to pcm mode 1 2 3 4 5 6 7 8 9 10 11 12 5 1 2 6 28 27 26 25 24 23 22 21 20 19 18 17 13 14 16 15
cs4397 24 ds333f1 6.0 pin description - 8x interpolator mode master clock - mclk pin 10, input function: the master clock frequency must be either 32x, 48x, 64x or 96x the input sample rate. table 8 illustrates the standard audio sample rates and the required master clock frequencies. bit clock - bcki pin 11, input function: clocks the individual serial data bits into the dil and dir pins. refer to figure 33 word clock - wcki pin 12, input function: the word clock determines which channel is currently being input on the serial audio data input, sdata. the frequency of the word clock must be at 8x the baseband sample rate. refer to figure 33. serial audio data - dir and dil pins 12 and 13, inputs function: two's complement msb-first serial data is input on these pins. the data is clocked into dil and dir via the bit clock. refer to figure 33. sample rate (khz) mclk (mhz) 32x 48x 64x 96x 32 x 8 8.1920 12.2880 16.384 24.576 44.1 x 8 11.2896 16.9344 22.579 33.869 48 x 8 12.2880 18.4320 24.576 36.864 table 8. common clock frequencies refer to pcm mode rst vref refer to pcm mode refer to pcm mode m4(ad0/cs) filt+ refer to pcm mode refer to pcm mode m3(ad1/cdin) filt- refer to pcm mode refer to pcm mode m2(scl/cclk) cmout refer to pcm mode refer to pcm mode m0(sda/cdout) aoutl- refer to pcm mode refer to pcm mode dgnd aoutl+ refer to pcm mode refer to pcm mode vd va refer to pcm mode refer to pcm mode vd agnd refer to pcm mode refer to pcm mode dgnd aoutr+ refer to pcm mode master clock mclk aoutr- refer to pcm mode bit clock bcki agnd refer to pcm mode word clock wcki mutec refer to pcm mode left channel data dil c/h refer to pcm mode right channel data dir mute refer to pcm mode 1 2 3 4 5 6 7 8 9 10 11 12 5 1 2 6 28 27 26 25 24 23 22 21 20 19 18 17 13 14 16 15
cs4397 ds333f1 25 7.0 applications 7.1 recommended power-up sequence 1. hold rst low until the power supplies, master, and left/right clocks are stable. 2. bring rst high.
cs4397 26 ds333f1 8.0 control port interface the control port is used to load all the internal settings of the cs4397. the operation of the control port may be completely asynchronous to th e audio sample rate. however, to avoid potential interference prob- lems, the control port pins should rema in static if no operation is required. the control port has 2 modes: spi and i 2 c, with the cs4397 operating as a slave device in both modes. if i 2 c operation is desired, ad0/cs should be tied to vd or dgnd. if the cs4397 ever detects a high to low transition on ad0/cs after power-up, spi mode will be selected. 8.1 spi mode in spi mode, cs is the cs4397 chip select signal, cclk is the control port bit clock, cdin is the input data line from the microcontroller, cdout is the data output and the chip address is 0010000. the data is clocked on the rising edge of cclk. figure 7 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first 7 bits on cdin form the chip address, and must be 0010000. the eighth bit is a read/write indicator (r/w ). the next 8 bits form the memory address pointer (map), which is set to 01h. the next 8 bits are the data which will be placed into the register designated by the map. 8.2 i 2 c mode in i 2 c mode, sda is a bi-directional data line. data is clocked into and out of the part by the clock, scl, with the clock to data relationship as shown in figure 3. there is no cs pin. pins ad0 and ad1 form the partial chip address and should be tied to vd or dgnd as required. the 7-bit address field, which is the first byte sent to the cs4397, must be 00100(ad1)(ad0) where (ad1) and (ad0) match the setting of the ad0 and ad1 pins. the eighth bit of the address byte is the r/w bit (high for a read, low for a write). if the operation is a write, the next byte is the memory address pointer, map, which selects the register to be read or written. the map is then followed by the data to be written. if the operation is a read, then the contents of the register pointed to by the map will be output after the chip address. for more information on i 2 c, please see ?the i 2 c-bus specification: version 2.0?, listed in the references section. memory address pointer (map) incr (auto map increment enable) map0-2 (memory address pointer) default = ?0? default = ?001? 0 - disabled 1 - enabled 76543210 incr reserved reserved reserved reserved map2 map1 map0 00000001
cs4397 ds333f1 27 map msb lsb data byte 1 byte n r/w map = memory address pointer = 0 address chip cdin cclk cs 0010000 figure 7. control port timing, spi mode sda scl 001000 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 8. control port timing, i 2 c mode
cs4397 28 ds333f1 m4 m1 (dif1) m0 (dif0) description format figure 00 0 left justified, up to 24-bit data 029 00 1 i 2 s, up to 24-bit data 130 01 0 right justified, 16-bit data 231 01 1 right justified, 24-bit data 333 table 9. single speed (16 to 50 khz) digital interface format options m4 m3 (dem1) m2 (dem0) description figure 00 0 32 khz de-emphasis 28 00 1 44.1 khz de-emphasis 28 01 0 48 khz de-emphasis 28 01 1 de-emphasis disabled - table 10. single speed (16 to 50 khz) de-emphasis options m4 m3 m2 m1 m0 description 11100 left justified up to 24-bit data, format 0 11101 i 2 s up to 24-bit data, format 1 11110 right justified 16-bit data, format 2 11111 right justified 24-bit data, format 3 table 11. double speed (50 to 100 khz) sample rate mode options m4 m3 m2 m1 m0 description 11000 left justified up to 24-bit data, format 0 11001 i 2 s up to 24-bit data, format 1 11010 right justified 16-bit data, format 2 11011 right justified 24-bit data, format 3 table 12. quad (100 to 200 khz) sample rate mode options m4 m3 m2 m1 m0 description 1000 (dir) 0 right justified 20-bit data 1000 (dir) 1 right justified 24-bit data table 13. 8x interpolated input mode options m4 m3 m2 m1 m0 description 1010 (dsd_r) 0 64x oversampled dsd 1010 (dsd_r) 1 128x oversampled dsd table 14. direct stream digital options
cs4397 ds333f1 29 -160 -140 -120 -100 -80 -60 -40 -20 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.6 frequency (normalized to fs) amplitude db 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.6 -160 -140 -120 -100 -80 -60 -40 -20 0 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 frequency (normalized to fs) amplitude db figure 9. single-speed transition band figure 10. single-speed stopband rejection -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 frequency (normalized to fs) amplitude db -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 frequency (normalized to fs) amplitude db figure 11. single-speed transition band figure 12. single-speed frequency response -140 -120 -100 -80 -60 -40 -20 0 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 frequency (normalized to fs) amplitude db -140 -120 -100 -80 -60 -40 -20 0 0.4 0.45 0.5 0.55 0.6 frequency (normalized to fs) amplitude db figure 13. double-speed stopband figure 14. double-speed transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.42 0.43 0.44 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 frequency (normalized to fs) amplitude db -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 frequency (normalized to fs) amplitude db figure 15. double-speed transition band figure 16. double-speed frequency response
cs4397 30 ds333f1 -160 -140 -120 -100 -80 -60 -40 -20 0 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 frequency (normalized to fs) amplitude db -160 -140 -120 -100 -80 -60 -40 -20 0 0.5 0.52 0.54 0.56 0.58 0.6 0.62 0.64 0.66 0.68 0.7 frequency (normalized to fs) amplitude db figure 17. quad-speed stopband rejection figure 18. quad-speed transition band -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 frequency (normalized to fs) amplitude db -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.35 0.37 0.39 0.41 0.43 0.45 0.47 0.49 0.51 0.53 frequency (normalized to fs) amplitude db figure 19. quad-speed transition band figure 20. quad-speed frequency response figure 21. 8x interpolator stop band figure 22. 8x interpolator transition band -140 -120 -100 -80 -60 -40 -20 0 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 frequency (normalized to fs) amplitude db .3 .4 .5 .6 .7 .8 .9 1.0 -120 -100 -80 -60 -40 -20 0 20 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 frequency (normalized to fs) amplitude db 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 6.4 .3 .4 .5 .6 .7 .8 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 frequency (normalized to fs) amplitude db 0 .05 .1 1.5 .2 .25 . 3 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 frequency (normalized to fs) amplitude db 2 2.4 2.8 3.2 3.6 4.0 4.4 4.8 .25 .3 3.5 4.0 4.5 5.0 5.5 6.0 figure 23. 8x interpolator transition band figure 24. 8x interpolator frequency response
cs4397 ds333f1 31 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 012345678910 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 2.5 3 3.5 4 4.5 5 5.5 6 frequency (normalized to fs) amplitude db figure 25. dsd frequency response figure 26. dsd transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 frequency (normalized to fs) amplitude db figure 27. dsd transition band figure 28. de-emphasis curve gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz
cs4397 32 ds333f1 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 29. format 0, left justified lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 30. format 1, i 2 s lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks figure 31. format 2, right justified, 16-bit data lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel figure 32. format 3, right justified, 24-bit data wcki bcki dil/dir lsb msb 23 22 21 20 8 3 21 lsb 4 7 6 5 13 12 11 10 14 9 18 17 16 15 19 figure 33. format 4, 8x interpolator mode
cs4397 ds333f1 33 9.0 parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10hz to 20khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 10.0 references 1) "how to achieve optimum performance from delta-sigma a/d & d/a converters" by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 2) cdb4397 evaluation board datasheet 3) ?the i 2 c-bus specification: version 2.0? philips semiconductors, december 1998. http://www.semiconductors.philips.com
cs4397 34 ds333f1 11.0 package dimensions inches millimeters dim min max min max a 0.093 0.104 2.35 2.65 a1 0.004 0.012 0.10 0.30 b 0.013 0.020 0.33 0.51 c 0.009 0.013 0.23 0.32 d 0.697 0.713 17.70 18.10 e 0.29g10 1 0.299 7.40 7.60 e 0.040 0.060 1.02 1.52 h 0.394 0.419 10.00 10.65 l 0.016 0.050 0.40 1.27 0 8 0 8 jedec #: ms-013 28l soic (300 mil body) package drawing d h e b a1 a c l seating plane 1 e

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